The present invention relates to a circuit for passively controlling the impedance of an integrated circuit node. More particularly, the present invention relates to a circuit for controlling the impedance of an integrated circuit node when the integrated circuit is in a power off condition.
It is desirable in many circumstances that the impedance of a particular node in an integrated circuit (i.e., the impedance of the integrated circuit between the node and a reference point such as ground) be controlled at times when the integrated circuit is not fully powered, such as when no source of power is applied to the power supply terminal of the integrated circuit, or when the integrated circuit is in a transient state immediately following the application or removal of a power source. For example, a system design may require that the output impedance of an integrated circuit line driver or reset circuit connected to an active line remain stable (e.g., low or high) when the line driver or reset circuit is not powered or is in a transient turn-on or turn-off condition.
In some integrated circuit devices, the output impedance of the device during power-off and transient conditions is a function of the impedance of an internal node. In such cases, it is necessary to control the impedance of the internal node during power-off conditions so that the output impedance of the device remains at a desired level. For example, the output stage of a typical integrated circuit device may include an output transistor having its collector connected to the output node of the device and its emitter connected to the ground node of the device, and a capacitor connected across the basecollector circuit of the transistor (e,g., for frequency compensation or to control slew rate). Under power-off conditions, it would be undesirable for the collector-emitter circuit of the transistor to conduct current, but such conduction may happen if, for example, an AC signal is applied to the output node of the device by external circuitry. The output transistor may conduct in this case because the frequency compensation capacitor couples the AC signal to the base of the output transistor and causes the transistor to turn on.
Attempts have been made in the past to control the power-off output impedance of such a circuit under AC signal conditions by including a capacitor or a parallel resistor-capacitor network between the base of the transistor and the ground node to lower the amount of current flowing back to the base of the transistor from the output node. These approaches suffer from several drawbacks. For example, if a capacitor alone is used, the charge build-up in the capacitor resulting from its conduction of current away from the base of the transistor may interfere with normal operation of the device during power-on conditions. If a parallel resistor is added to discharge the capacitor, the resistor not only must have a high resistance value to prevent it from interfering with normal circuit operation during power-on conditions, but must also be capable of conducting the potentially large discharge current of the capacitor. Such a resistor requires a large die area and thus is costly in terms of the space on an integrated circuit die which must be sacrificed to implement the resistor.
Another drawback is that the capacitor and the resistor-capacitor network do not compensate for the effect of increasing temperature on the transistor base-emitter turn-on voltage. As the operating temperature of the device increases, the base-emitter voltage required to turn on the transistor decreases. However, the degree to which the capacitor or the resistor-capacitor network connected across the base-emitter circuit attenuates an AC signal coupled to the base of the transistor does not increase with temperature. Thus at high operating temperatures the prior art capacitor and capacitor-resistor network become less effective at preventing the transistor from conducting current in response to an AC signal applied to the output node of the device, and therefore become less effective at controlling the output impedance of the device.
In discrete circuits, the problem of creating a low impedance node during power-off conditions has been solved by using a depletion-mode FET transistor to create a low impedance current path between the node and ground. During power-on conditions, a bias voltage is applied to the gate of the FET transistor which causes a depletion of the normally existing conducting channel. It would be desirable, however, to implement a circuit for controlling the impedance of an integrated circuit node in a monolithic integrated circuit.